Capgemini Recruiting Any Graduate/Any Postgraduate for the position ASIC / Design verification Eng .This position requires Any Graduate/Any Postgraduate with prior experience. Interested and eligible candidates have to apply with like arranged at bottom of this post. This vacancy available from 12th July 2022 and will expire soon .We are recommended to apply as earliest for early shortlist . Shortlisted candidates have to go through selection process( Test, Interview rounds ) for selection for the position.
Summary of Vacancy- ASIC / Design verification Eng
| Company Name | Capgemini |
| Location | Hyderabad/Secunderabad, Ahmedabad, Chennai, Bangalore(WFH during Covid) |
| Salary Offering | Not Disclosed |
| Hiring Designation | ASIC / Design verification Eng |
| Experience Required | 02-07+Years |
| Qualification | Any Graduate/Any Postgraduate |
| No Vacancy | Not Disclosed By Recruiter |
Interested candidates are please share updated resume to madhuri.sivaraju@capgemini.com or Call 9148451278
Job Role or Description
- Methodology: UVM Lang: System Verilog Good knowledge on protocols: Pcle, Ehernet,DDR etc Should have worked on GLS. Primary Skills Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl. Secondary Skills Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR.
Company Profile Capgemini is a global leader in partnering with companies to transform and manage their business by harnessing the power of technology. The Group is guided everyday by its purpose of unleashing human energy through technology for an inclusive and sustainable future. It is a responsible and diverse organization of over 300,000 team members in nearly 50 countries.
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